As semiconductor technologies evolve, a greater number of devices have been integrated into a single chip. A memory chip may comprise a plurality of transistors and capacitors. In accordance with the characteristics of data storage, semiconductor memory chips may be divided into two major types. One is volatile memory. The other is nonvolatile memory. Among nonvolatile memory chips, a static random access memory (SRAM) chip stores a bit of data in the state of a flip-flop. A dynamic random access memory (DRAM) chip stores a bit of data in a charge in a capacitor. SRAM is faster than DRAM, while SRAM may occupy a larger area than DRAM. Both SRAM chips and DRAM chips comprise various digital circuits synchronized by a variety of different clock signals. As semiconductor technologies further advances, the frequency of memory clock signals increases as well. As a result, the setup and hold time of a digital circuit in either a SRAM chip or a DRAM chip has become shorter.
In a synchronous circuit such as a positive edge triggered D type flip-flop, the setup time is defined as a minimum period in which a data signal is held steady before the leading edge of a clock signal is applied to the D type flip-flop. A valid and constant data signal during such a period can prevent the flip-flop from entering a metastable state in which the output of the D type flip-flop is not predictable. Furthermore, the output of the D type flip-flop may oscillate between a logic low state and a logic high state. Likewise, the hold time is defined as a period after the leading edge of the clock signal. Similarly, during the specified hold time, the data signal must be kept valid and constant so that the flip-flop can generate a valid output. The setup hold time of synchronous circuits may vary based upon different semiconductor processes. A typical setup and hold time may be less than one hundred picoseconds.
In order to avoid metastability induced by lack of enough setup and hold time, the setup and hold time of a synchronous circuit may be characterized and published as supporting information. Based upon measured setup and hold time, the user of synchronous circuits can provide a clock signal having appropriate timing skew. There are a variety of test systems available for characterizing the setup and hold time of synchronous circuits. However, a conventional tester may not provide a resolution in a range of approximately one hundred picoseconds.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.